Phase-locked loops (PLLs) are used extensively in electronic circuits to generate a signal that has a fixed relation to the phase of a reference signal. A PLL circuit raises or lowers the frequency of a controlled oscillator signal until it matches the reference signal in both frequency and phase. Phase-locked loops are widely used in electronic applications to, for example, generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs.
In conventional PLL circuits, all PLL components operate at the same voltage supply level. Thus, an oscillator providing a reference signal, a phase frequency detector, a charge pump, low pass loop filter, voltage-controlled oscillator (VCO), and frequency divider all may operate at, for example, 3.3 volts. However, in a more recent deep sub-micron process, the operating voltages of all the digital blocks can be reduced, e.g. to around 1 volt, to save power while achieving higher speed. These digital blocks can include the frequency divider, prescaler, phase frequency detector, VCO, and reference signal oscillator. A higher voltage, however, is still desired as the operating voltage for the charge pump to minimize jitter, noise, leakage, and linearity distortion, and to achieve a high tuning range for the VCO.
To allow the charge pump to operate at a higher voltage level, an open drain circuit or a cross-coupled voltage level shifter is typically used to convert the low voltage control signals from the phase frequency detector to a higher voltage level that controls the charge pump. However, the low speed performance of voltage level shifters may cause large jitter and noise in the PLL circuit. Likewise, an open drain circuit is a significant contributor of jitter and noise in the PLL. Other designs compromise the optimization by requiring that all components of the PLL circuit function at the same voltage level, either at the higher voltage or at the lower voltage.
Accordingly, a system and method that operates a charge pump in a PLL circuit at higher voltage while operating other components of the PLL circuit at a lower voltage without significantly increasing jitter and noise in the PLL circuit, would be desirable in many applications.